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When trained as generative models, Deep Learning algorithms have shownexceptional performance on tasks involving high dimensional data such as imagedenoising and super-resolution. In an increasingly connected world dominated bymobile and edge devices, there is surging demand for these algorithms to runlocally on embedded platforms. FPGAs, by virtue of their reprogrammability andlow-power characteristics, are ideal candidates for these edge computingapplications. As such, we design a spatio-temporally parallelized hardwarearchitecture capable of accelerating a deconvolution algorithm optimized forpower-efficient inference on a resource-limited FPGA. We propose thisFPGA-based accelerator to be used for Deconvolutional Neural Network (DCNN)inference in low-power edge computing applications. To this end, we developmethods that systematically exploit micro-architectural innovations, designspace exploration, and statistical analysis. Using a Xilinx PYNQ-Z2 FPGA, weleverage our architecture to accelerate inference for two DCNNs trained on theMNIST and CelebA datasets using the Wasserstein GAN framework. On thesenetworks, our FPGA design achieves a higher throughput to power ratio withlower run-to-run variation when compared to the NVIDIA Jetson TX1 edgecomputing GPU.

A Competitive Edge: Can FPGAs Beat GPUs at DCNN Inference Acceleration in Resource-Limited Edge Computing Applications?