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The lack of an easily realizable complementary circuit technology offeringlow static power consumption has been limiting the utilization of othersemiconductor materials than silicon. In this publication, a novel depletionmode JFET based complementary circuit technology is presented and herein afterreferred to as Complementary Semiconductor (CS) circuit technology. The factthat JFETs are pure semiconductor devices, i.e. a carefully optimized MetalOxide Semiconductor (MOS) gate stack is not required, facilitates theimplementation of CS circuit technology to many semiconductor materials, likee.g. germanium and silicon carbide. Furthermore, when the CS circuit technologyis idle there are neither conductive paths between nodes that are biased atdifferent potentials nor forward biased p-n junctions and thus it enables lowstatic power consumption. Moreover, the fact that the operation of depletionmode JFETs does not necessitate the incorporation of forward biased p-njunctions means that CS circuit technology is not limited to wide band-gapsemiconductor materials, low temperatures, and/or low voltage spans. In thispaper the operation of the CS logic is described and proven via simulations.

Novel depletion mode JFET based low static power complementary circuit technology