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We propose a co-design approach for compute-in-memory inference for deepneural networks (DNN). We use multiplication-free function approximators basedon ell_1 norm along with a co-adapted processing array and compute flow. Usingthe approach, we overcame many deficiencies in the current art of in-SRAM DNNprocessing such as the need for digital-to-analog converters (DACs) at eachoperating SRAM row/column, the need for high precision analog-to-digitalconverters (ADCs), limited support for multi-bit precision weights, and limitedvector-scale parallelism. Our co-adapted implementation seamlessly extends tomulti-bit precision weights, it doesn't require DACs, and it easily extends tohigher vector-scale parallelism. We also propose an SRAM-immersed successiveapproximation ADC (SA-ADC), where we exploit the parasitic capacitance of bitlines of SRAM array as a capacitive DAC. Since the dominant area overhead inSA-ADC comes due to its capacitive DAC, by exploiting the intrinsic parasiticof SRAM array, our approach allows low area implementation of within-SRAMSA-ADC. Our 8$\times$62 SRAM macro, which requires a 5-bit ADC, achieves$\sim$105 tera operations per second per Watt (TOPS/W) with 8-bit input/weightprocessing at 45 nm CMOS.

MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference using Memory-immersed Data Conversion and Multiplication-free Operators