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With the growing demands of consumer electronic products, the computationalrequirements are increasing exponentially. Due to the applications'computational needs, the computer architects are trying to pack as many coresas possible on a single die for accelerated execution of the applicationprogram codes. In a multiprocessor system-on-chip (MPSoC), striking a balanceamong the number of cores, memory subsystems, and network-on-chip parameters isessential to attain the desired performance. In this paper, we presentANDROMEDA, a RISC-V based framework that allows us to explore the differentconfigurations of an MPSoC and observe the performance penalties and gains. Weemulate the various configurations of MPSoC on the Synopsys HAPS-80D Dual FPGAplatform. Using STREAM, matrix multiply, and N-body simulations as benchmarks,we demonstrate our framework's efficacy in quickly identifying the rightparameters for efficient execution of these benchmarks.

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework