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In this paper, first, a hardware-friendly pruning algorithm for reducingenergy consumption and improving the speed of Long Short-Term Memory (LSTM)neural network accelerators is presented. Next, an FPGA-based platform forefficient execution of the pruned networks based on the proposed algorithm isintroduced. By considering the sensitivity of two weight matrices of the LSTMmodels in pruning, different sparsity ratios (i.e., dual-ratio sparsity) areapplied to these weight matrices. To reduce memory accesses, a row-wisesparsity pattern is adopted. The proposed hardware architecture makes use ofcomputation overlapping and pipelining to achieve low-power and high-speed. Theeffectiveness of the proposed pruning algorithm and accelerator is assessedunder some benchmarks for natural language processing, binary sentimentclassification, and speech recognition. Results show that, e.g., compared to arecently published work in this field, the proposed accelerator could provideup to 272% higher effective GOPS/W and the perplexity error is reduced by up to1.4% for the PTB dataset.

BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification