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This paper presents a workflow for synthesizing near-optimal FPGAimplementations for structured-mesh based stencil applications for explicitsolvers. It leverages key characteristics of the application class, itscomputation-communication pattern, and the architectural capabilities of theFPGA to accelerate solvers from the high-performance computing domain. Key newfeatures of the workflow are (1) the unification of standard state-of-the-arttechniques with a number of high-gain optimizations such as batching andspatial blocking/tiling, motivated by increasing throughput for real-world workloads and (2) the development and use of a predictive analytic model forexploring the design space, resource estimates and performance. Threerepresentative applications are implemented using the design workflow on aXilinx Alveo U280 FPGA, demonstrating near-optimal performance and over 85%predictive model accuracy. These are compared with equivalent highly-optimizedimplementations of the same applications on modern HPC-grade GPUs (Nvidia V100)analyzing time to solution, bandwidth and energy consumption. Performanceresults indicate equivalent runtime performance of the FPGA implementations tothe V100 GPU, with over 2x energy savings, for the largest non-trivialapplication synthesized on the FPGA compared to the best performing GPU-basedsolution. Our investigation shows the considerable challenges in gaining highperformance on current generation FPGAs compared to traditional architectures.We discuss determinants for a given stencil code to be amenable to FPGAimplementation, providing insights into the feasibility and profitability of adesign and its resulting performance.

High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers