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The analog front-end for the Low Gain Avalanche Detector (LGAD) basedprecision timing application in the CMS Endcap Timing Layer (ETL) has beenprototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very firstprototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate theperformance of the analog frontend, with the goal to achieve 40 to 50 ps timeresolution per hit with LGAD (therefore reach about 30ps per track with twodetector-layer hits per track). ETROC0 consists of preamplifier anddiscriminator stages, which amplifies the LGAD signal and generates digitalpulses containing time of arrival and time over threshold information. Thispaper will focus on the design considerations that lead to the ETROC front-endarchitecture choice, the key design features of the building blocks, themethodology of using the LGAD simulation data to evaluate and optimize thefront-end design. The ETROC0 prototype chips have been extensively tested usingcharge injection and the measured performance agrees well with simulation. Theinitial beam test results are also presented, with time resolution of around 33ps observed from the preamplifier waveform analysis and around 41 ps from thediscriminator pulses analysis. A subset of ETROC0 chips have also been testedto a total ionizing dose of 100 MRad with X-ray and no performance degradationbeen observed.

The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL