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This paper obtains fundamental limits on the computational precision ofin-memory computing architectures (IMCs). An IMC noise model and associated SNRmetrics are defined and their interrelationships analyzed to show that theaccuracy of IMCs is fundamentally limited by the compute SNR($\text{SNR}_{\text{a}}$) of its analog core, and that activation, weight andoutput precision needs to be assigned appropriately for the final output SNR$\text{SNR}_{\text{T}} \rightarrow \text{SNR}_{\text{a}}$. The minimumprecision criterion (MPC) is proposed to minimize the ADC precision. Threein-memory compute models - charge summing (QS), current summing (IS) and chargeredistribution (QR) - are shown to underlie most known IMCs. Noise, energy anddelay expressions for the compute models are developed and employed to deriveexpressions for the SNR, ADC precision, energy, and latency of IMCs. Thecompute SNR expressions are validated via Monte Carlo simulations in a 65 nmCMOS process. For a 512 row SRAM array, it is shown that: 1) IMCs have an upperbound on their maximum achievable $\text{SNR}_{\text{a}}$ due to constraints onenergy, area and voltage swing, and this upper bound reduces with technologyscaling for QS-based architectures; 2) MPC enables $\text{SNR}_{\text{T}}\rightarrow \text{SNR}_{\text{a}}$ to be realized with minimal ADC precision;3) QS-based (QR-based) architectures are preferred for low (high) compute SNRscenarios.

Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications