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This paper presents Systolic-CNN, an OpenCL-defined scalable,run-time-flexible FPGA accelerator architecture, optimized for accelerating theinference of various convolutional neural networks (CNNs) in multi-tenancycloud/edge computing. The existing OpenCL-defined FPGA accelerators for CNNinference are insufficient due to limited flexibility for supporting multipleCNN models at run time and poor scalability resulting in underutilized FPGAresources and limited computational parallelism. Systolic-CNN adopts a highlypipelined and paralleled 1-D systolic array architecture, which efficientlyexplores both spatial and temporal parallelism for accelerating CNN inferenceon FPGAs. Systolic-CNN is highly scalable and parameterized, which can beeasily adapted by users to achieve up to 100% utilization of the coarse-grainedcomputation resources (i.e., DSP blocks) for a given FPGA. Systolic-CNN is alsorun-time-flexible in the context of multi-tenancy cloud/edge computing, whichcan be time-shared to accelerate a variety of CNN models at run time withoutthe need of recompiling the FPGA kernel hardware nor reprogramming the FPGA.The experiment results based on an Intel Arria/Stratix 10 GX FPGA Developmentboard show that the optimized single-precision implementation of Systolic-CNNcan achieve an average inference latency of 7ms/2ms, 84ms/33ms, 202ms/73ms,1615ms/873ms, and 900ms/498ms per image for accelerating AlexNet, ResNet-50,ResNet-152, RetinaNet, and Light-weight RetinaNet, respectively. Codes areavailable at https://github.com/PSCLab-ASU/Systolic-CNN.

Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA  Accelerator Architecture for Accelerating Convolutional Neural Network  Inference in Cloud/Edge Computing