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In this work, we present a simplification and a corresponding hardwarearchitecture for hard-decision recursive projection-aggregation (RPA) decodingof Reed-Muller (RM) codes. In particular, we transform the recursive structureof RPA decoding into a simpler and iterative structure with minimalerror-correction degradation. Our simulation results for RM(7,3) show that theproposed simplification has a small error-correcting performance degradation(0.005 in terms of channel crossover probability) while reducing the averagenumber of computations by up to 40%. In addition, we describe the first fullyparallel hardware architecture for simplified RPA decoding. We present FPGAimplementation results for an RM(6,3) code on a Xilinx Virtex-7 FPGA showingthat our proposed architecture achieves a throughput of 171 Mbps at a frequencyof 80 MHz.

Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes