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This brief proposes a hardware implementation architecture for Fano decodingof polarization-adjusted convolutional (PAC) codes. This architecture uses anovel branch metric unit specific to PAC codes. The proposed decoder is testedon FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 Vlibrary. The decoder can be clocked at 500 MHz and reach an average informationthroughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128and a code rate of 1/2.

Hardware Implementation of Fano Decoder for Polarization-adjusted Convolutional (PAC) Codes