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Many hardware vendors have introduced specialized deep neural networks (DNN)accelerators owing to their superior performance and efficiency. As such, howto generate and optimize the code for the hardware accelerator becomes animportant yet less explored problem. In this paper, we perform thecompiler-stage optimization study using a novel and representative CambriconDNN accelerator and demonstrate that the code optimization knobs play animportant role in unleashing the potential of hardware computationalhorsepower. However, even only two studied code optimization knobs, namely thenumber of cores and layer fusion scheme, present an enormous search space thatprevents the naive brute-force search. This work introduces a joint,auto-tuning optimization framework to address this challenge. We first use aset of synthesized DNN layers to study the interplay between the hardwareperformance and layer characteristics. Based on the insights, we extract theoperation count and feature map channel size as each layer's characteristicsand derive a joint optimization strategy to decide the performance-optimal corenumber and fusion scheme. We evaluate the performance of the proposed approachusing a set of representative DNN models and show that it achieves the minimalof 3.6x and the maximal of 7.9x performance speedup compared to no optimizationbaseline. We also show that the achieved speedup is close to the oracle casethat is based on a reduced brute-force search but with much less search time.

DLFusion: An Auto-Tuning Compiler for Layer Fusion on Deep Neural Network Accelerator