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Manycore processors feature a high number of general-purpose cores designedto work in a multithreaded fashion. Recent manycore processors are keptcoherent using scalable distributed directories. A paramount example is theIntel Mesh interconnect, which consists of a network-on-chip interconnecting"tiles", each of which contains computation cores, local caches, and coherencemasters. The distributed coherence subsystem must be queried for everyout-of-tile access, imposing an overhead on memory latency. This paper studiesthe physical layout of an Intel Knights Landing processor, with a particularfocus on the coherence subsystem, and uncovers the pseudo-random mappingfunction of physical memory blocks across the pieces of the distributeddirectory. Leveraging this knowledge, candidate optimizations to improve memorylatency through the minimization of coherence traffic are studied. Althoughthese optimizations do improve memory throughput, ultimately this does nottranslate into performance gains due to inherent overheads stemming from thecomputational complexity of the mapping functions.

Coherence Traffic in Manycore Processors with Opaque Distributed Directories