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RISC-V, an open instruction set architecture, is getting the attention ofsoft processor developers. Implementing only a basic 32-bit integer instructionset of RISC-V, which is defined as RV32I, might be satisfactory for embeddedsystems. However, multiplication and division instructions are not present inRV32I, rather than defined as M-extension. Several research projects haveproposed both RV32I and RV32IM processor. However, there is no indication ofhow much performance can be improved by adding M-extension to RV32I. In otherwords, when we should consider adding M-extension into the soft processor andhow much hardware resource requirements will increase.  In this paper, we propose an extension of the RVCoreP soft processor (whichimplements RV32I instruction set only) to support RISC-V M-extensioninstructions. A simple fork-join method is used to expand the executioncapability to support M-extension instructions as well as a possible futureenhancement. We then perform the benchmark using Dhrystone, Coremark, andEmbench programs. We found that RV32IM is 1.87 and 3.13 times better inperformance for radix-4 and DSP multiplier, respectively. In addition to that,our RV32IM implementation is 13\% better than the equivalent RISC-V processor.

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors