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With transistor scaling reaching its limits, interposer-based integration ofdies (chiplets) is gaining traction. Such an interposer-based integrationenables finer and tighter interconnect pitch than traditionalsystem-on-packages and offers two key benefits: 1. It reduces design-to-markettime by bypassing the time-consuming process of verification and fabrication.2. It reduces the design cost by reusing chiplets. While black-boxing of theslow design stages cuts down the design time, it raises significant securityconcerns. We study the security implications of the emerging interposer-basedintegration methodology. The black-boxed design stages deploy security measuresagainst hardware Trojans, reverse engineering, and intellectual property piracyin traditional systems-on-chip (SoC) designs and hence are not suitable forinterposer-based integration. We propose using functionally diverse chiplets todetect and thwart hardware Trojans and use the inherent logic redundancy toshore up anti-piracy measures. Our proposals do not rely on access to theblack-box design stages. We evaluate the security, time and cost benefits ofour plan by implementing a MIPS processor, a DCT core, and an AES core usingvarious IPs from the Xilinx CORE GENERATOR IP catalog, on an interposer-basedXilinx FPGA.

Security Assessment of Interposer-based Chiplet Integration