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In this paper, we propose a very compact embedded CNN processor design basedon a modified logarithmic computing method using very low bit-widthrepresentation. Our high-quality CNN processor can easily fit into edgedevices. For Yolov2, our processing circuit takes only 0.15 mm2 using TSMC 40nm cell library. The key idea is to constrain the activation and weight valuesof all layers uniformly to be within the range [-1, 1] and produce lowbit-width logarithmic representation. With the uniform representations, wedevise a unified, reusable CNN computing kernel and significantly reducecomputing resources. The proposed approach has been extensively evaluated onmany popular image classification CNN models (AlexNet, VGG16, and ResNet-18/34)and object detection models (Yolov2). The hardware-implemented results showthat our design consumes only minimal computing and storage resources, yetattains very high accuracy. The design is thoroughly verified on FPGAs, and theSoC integration is underway with promising results. With extremely efficientresource and energy usage, our design is excellent for edge computing purposes.

A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing