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Graphics Processing Units (GPUs) employ large register files to accommodateall active threads and accelerate context switching. Unfortunately, registerfiles are a scalability bottleneck for future GPUs due to long access latency,high power consumption, and large silicon area provisioning. Prior workproposes hierarchical register file to reduce the register file powerconsumption by caching registers in a smaller register file cache.Unfortunately, this approach does not improve register access latency due tothe low hit rate in the register file cache.  In this paper, we propose the Latency-Tolerant Register File (LTRF)architecture to achieve low latency in a two-level hierarchical structure whilekeeping power consumption low. We observe that compile-time interval analysisenables us to divide GPU program execution into intervals with an accurateestimate of a warp's aggregate register working-set within each interval. Thekey idea of LTRF is to prefetch the estimated register working-set from themain register file to the register file cache under software control, at thebeginning of each interval, and overlap the prefetch latency with the executionof other warps. We observe that register bank conflicts while prefetching theregisters could greatly reduce the effectiveness of LTRF. Therefore, we devisea compile-time register renumbering technique to reduce the likelihood ofregister bank conflicts. Our experimental results show that LTRF enableshigh-capacity yet long-latency main GPU register files, paving the way forvarious optimizations. As an example optimization, we implement the mainregister file with emerging high-density high-latency memory technologies,enabling 8X larger capacity and improving overall GPU performance by 34%.

Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation