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Plenty of research efforts have been devoted to FPGA-based acceleration, dueto its low latency and high energy efficiency. However, using the originallow-level hardware description languages like Verilog to program FPGAs requiresgenerally good knowledge of hardware design details and hand-on experiences.Fortunately, the FPGA community intends to address this low programmabilityissues. For example, , with the intention that programming FPGAs is just aseasy as programming GPUs. Even though Vitis is proven to increaseprogrammability, we cannot directly obtain high performance without carefuldesign regarding hardware pipeline and memory subsystem.In this paper, we focuson the memory subsystem, comprehensively and systematically benchmarking theeffect of optimization methods on memory performance. Upon benchmarking, wequantitatively analyze the typical memory access patterns for a broad range ofapplications, including AI, HPC, and database. Further, we also provide thecorresponding optimization direction for each memory access pattern so as toimprove overall performance.

Optimizing Memory Performance of Xilinx FPGAs under Vitis