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Deep neural networks have become the standard approach to building reliableNatural Language Processing (NLP) applications, ranging from Neural MachineTranslation (NMT) to dialogue systems. However, improving accuracy byincreasing the model size requires a large number of hardware computations,which can slow down NLP applications significantly at inference time. Toaddress this issue, we propose a novel vector-vector-matrix architecture(VVMA), which greatly reduces the latency at inference time for NMT. Thisarchitecture takes advantage of specialized hardware that has low-latencyvector-vector operations and higher-latency vector-matrix operations. It alsoreduces the number of parameters and FLOPs for virtually all models that relyon efficient matrix multipliers without significantly impacting accuracy. Wepresent empirical results suggesting that our framework can reduce the latencyof sequence-to-sequence and Transformer models used for NMT by a factor offour. Finally, we show evidence suggesting that our VVMA extends to otherdomains, and we discuss novel hardware for its efficient use.

Vector-Vector-Matrix Architecture: A Novel Hardware-Aware Framework for Low-Latency Inference in NLP Applications