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ATLAS detector at the LHC will undergo a major Phase-II upgrade for the HighLuminosity LHC. The upgrade affects all major ATLAS systems, including theTrigger and Data Acquisition systems. As part of the Level-0 Trigger System,the Global Trigger uses full-granularity calorimeter cells to performalgorithms, refines the trigger objects and applies topological requirements.The Global Trigger uses a Global Common Module as the building block of itsdesign. To achieve a high input and output bandwidth and substantial processingpower, the Global Common Module will host the most advanced FPGAs and opticalmodules. In order to evaluate the new generation of optical modules and FPGAsrunning at high data rates (up to 28 Gb/s), a Global Trigger TechnologicalDemonstrator board has been designed and tested. The main hardware blocks ofthe board are the Xilinx Virtex Ultrascale+ 9P FPGA and a number of opticalmodules, including high-speed Finisar BOA and Samtec FireFly modules. Long-runlink tests have been performed for the Finisar BOA and Samtec FireFly opticalmodules running at 25.65 and 27.58 Gb/s respectively. Successful resultsdemonstrating a good performance of the optical modules when communicating withthe FPGA have been obtained. The paper provides a hardware overview andmeasurement results of the Technological Demonstrator.

Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade