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Low bit-width Quantized Neural Networks (QNNs) enable deployment of complexmachine learning models on constrained devices such as microcontrollers (MCUs)by reducing their memory footprint. Fine-grained asymmetric quantization (i.e.,different bit-widths assigned to weights and activations on a tensor-by-tensorbasis) is a particularly interesting scheme to maximize accuracy under a tightmemory constraint. However, the lack of sub-byte instruction set architecture(ISA) support in SoA microprocessors makes it hard to fully exploit thisextreme quantization paradigm in embedded MCUs. Support for sub-byte andasymmetric QNNs would require many precision formats and an exorbitant amountof opcode space. In this work, we attack this problem with status-based SIMDinstructions: rather than encoding precision explicitly, each operand'sprecision is set dynamically in a core status register. We propose a novelRISC-V ISA core MPIC (Mixed Precision Inference Core) based on the open-sourceRI5CY core. Our approach enables full support for mixed-precision QNN inferencewith different combinations of operands at 16-, 8-, 4- and 2-bit precision,without adding any extra opcode or increasing the complexity of the decodestage. Our results show that MPIC improves both performance and energyefficiency by a factor of 1.1-4.9x when compared to software-basedmixed-precision on RI5CY; with respect to commercially available Cortex-M4 andM7 microcontrollers, it delivers 3.6-11.7x better performance and 41-155xhigher efficiency.

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference