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The capacity of offloading data and control tasks to the network is becomingincreasingly important, especially if we consider the faster growth of networkspeed when compared to CPU frequencies. In-network compute alleviates the hostCPU load by running tasks directly in the network, enabling additionalcomputation/communication overlap and potentially improving overall applicationperformance. However, sustaining bandwidths provided by next-generationnetworks, e.g., 400 Gbit/s, can become a challenge. sPIN is a programming modelfor in-NIC compute, where users specify handler functions that are executed onthe NIC, for each incoming packet belonging to a given message or flow. Itenables a CUDA-like acceleration, where the NIC is equipped with lightweightprocessing elements that process network packets in parallel. We investigatethe architectural specialties that a sPIN NIC should provide to enablehigh-performance, low-power, and flexible packet processing. We introducePsPIN, a first open-source sPIN implementation, based on a multi-cluster RISC-Varchitecture and designed according to the identified architecturalspecialties. We investigate the performance of PsPIN with cycle-accuratesimulations, showing that it can process packets at 400 Gbit/s for several usecases, introducing minimal latencies (26 ns for 64 B packets) and occupying atotal area of 18.5 mm 2 (22 nm FDSOI).

PsPIN: A high-performance low-power architecture for flexible in-network compute