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As machine learning spreads into more and more application areas, microcontrollers and low power CPUs are increasingly being used to perform inferencewith machine learning models. The capability to deploy onto these limitedhardware targets is enabling machine learning models to be used across adiverse range of new domains. Optimising the inference process on these targetsposes different challenges from either desktop CPU or GPU implementations,where the small amounts of RAM available on these targets sets limits on sizeof models which can be executed. Analysis of the memory use patterns of elevenmachine learning models was performed. Memory load and store patterns wereobserved using a modified version of the Valgrind debugging tool, identifyingmemory areas holding values necessary for the calculation as inferenceprogressed. These analyses identified opportunities optimise the memory use ofthese models by overlapping the input and output buffers of individual tensoroperations. Three methods are presented which can calculate the safe overlap ofinput and output buffers for tensor operations. Ranging from a computationallyexpensive approach with the ability to operate on compiled layer operations, toa versatile analytical solution which requires access to the original sourcecode of the layer. The diagonal memory optimisation technique is described andshown to achieve memory savings of up to 34.5% when applied to eleven commonmodels. Micro-controller targets are identified where it is only possible todeploy some models if diagonal memory optimisation is used.

Diagonal Memory Optimisation for Machine Learning on Micro-controllers