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Convolutional Neural Networks (CNNs) have proven to be extremely accurate forimage recognition, even outperforming human recognition capability. Whendeployed on battery-powered mobile devices, efficient computer architecturesare required to enable fast and energy-efficient computation of costlyconvolution operations. Despite recent advances in hardware accelerator designfor CNNs, two major problems have not yet been addressed effectively,particularly when the convolution layers have highly diverse structures: (1)minimizing energy-hungry off-chip DRAM data movements; (2) maximizing theutilization factor of processing resources to perform convolutions. This workthus proposes an energy-efficient architecture equipped with several optimizeddataflows to support the structural diversity of modern CNNs. The proposedapproach is evaluated by implementing convolutional layers of VGGNet-16 andResNet-50. Results show that the architecture achieves a Processing Element(PE) utilization factor of 98% for the majority of 3x3 and 1x1 convolutionallayers, while limiting latency to 396.9 ms and 92.7 ms when performingconvolutional layers of VGGNet-16 and ResNet-50, respectively. In addition, theproposed architecture benefits from the structured sparsity in ResNet-50 toreduce the latency to 42.5 ms when half of the channels are pruned.

CARLA: A Convolution Accelerator with a Reconfigurable and Low-Energy Architecture