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The use of reconfigurable computing, and FPGAs in particular, has strongpotential in the field of High Performance Computing (HPC). However thetraditionally high barrier to entry when it comes to programming thistechnology has, until now, precluded widespread adoption. To popularisereconfigurable computing with communities such as HPC, Xilinx have recentlyreleased the first version of Vitis, a platform aimed at making the programmingof FPGAs much more a question of software development rather than hardwaredesign. However a key question is how well this technology fulfils the aim, andwhether the tooling is mature enough such that software developers using FPGAsto accelerate their codes is now a more realistic proposition, or whether itsimply increases the convenience for existing experts. To examine this questionwe use the Himeno benchmark as a vehicle for exploring the Vitis platform forbuilding, executing and optimising HPC codes, describing the different stepsand potential pitfalls of the technology. The outcome of this exploration is ademonstration that, whilst Vitis is an excellent step forwards andsignificantly lowers the barrier to entry in developing codes for FPGAs, it isnot a silver bullet and an underlying understanding of dataflow stylealgorithmic design and appreciation of the architecture is still key toobtaining good performance on reconfigurable architectures.

Weighing up the new kid on the block: Impressions of using Vitis for HPC software development