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Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAM inon-chip caches due to several advantages. These advantages includenon-volatility, low leakage, high integration density, and CMOS compatibility.Prior studies have shown that relaxing and adapting the STTRAM retention timeto runtime application needs can substantially reduce overall cache energywithout significant latency overheads, due to the lower STTRAM write energy andlatency in shorter retention times. In this paper, as a first step towardsefficient prefetching across the STTRAM cache hierarchy, we study prefetchingin reduced retention STTRAM L1 caches. Using SPEC CPU 2017 benchmarks, weanalyze the energy and latency impact of different prefetch distances indifferent STTRAM cache retention times for different applications. We show thatexpired_unused_prefetches---the number of unused prefetches expired by thereduced retention time STTRAM cache---can accurately determine the bestretention time for energy consumption and access latency. This new metric canalso provide insights into the best prefetch distance for memory bandwidthconsumption and prefetch accuracy. Based on our analysis and insights, wepropose Prefetch-Aware Retention time Tuning (PART) and Retention time-basedPrefetch Control (RPC). Compared to a base STTRAM cache, PART and RPCcollectively reduced the average cache energy and latency by 22.24% and 24.59%,respectively. When the base architecture was augmented with thestate-of-the-art near-side prefetch throttling (NST), PART+RPC reduced theaverage cache energy and latency by 3.50% and 3.59%, respectively, and reducedthe hardware overhead by 54.55%

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches