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This article starts from the assumption that near future 100BTransistorSuperComputers-on-a-Chip will include N big multi-core processors, 1000N smallmany-core processors, a TPU-like fixed-structure systolic array accelerator forthe most frequently used Machine Learning algorithms needed in bandwidth-boundapplications and a flexible-structure reprogrammable accelerator for lessfrequently used Machine Learning algorithms needed in latency-criticalapplications.

The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing