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Optimally mapping a parallel application to compute and communicationresources is increasingly important as both system size and heterogeneityincrease. A similar mapping problem exists in gate-based quantum computingwhere the objective is to map tasks to gates in a topology-aware fashion. Thisis an NP-complete graph isomorphism problem, and existing task assignmentapproaches are either heuristic or based on physical optimization algorithms,providing different speed and solution quality trade-offs. Ising machines suchas quantum and digital annealers have recently become available and offer analternative hardware solution to solve this type of optimization problems. Inthis paper, we propose an algorithm that allows solving the topology-awareassignment problem using Ising machines. We demonstrate the algorithm on twouse cases, i.e. classical task scheduling and quantum circuit gate scheduling.TIGER---topology-aware task/gate assignment mapper tool---implements ourproposed algorithms and automatically integrates them into the quantum softwareenvironment. To address the limitations of physical solver, we propose andimplement a domain-specific partition strategy that allows solving larger-scaleproblems and a weight optimization algorithm that allows tuning Ising modelparameters to achieve better restuls. We use D-Wave's quantum annealer todemonstrate our algorithm and evaluate the proposed tool flow in terms ofperformance, partition efficiency, and solution quality. Results showsignificant speed-up compared to classical solutions, better scalability, andhigher solution quality when using TIGER together with the proposed partitionmethod. It reduces the data movement cost by 68\% in average for quantumcircuit assignment compared to the IBM QX optimizer.

TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates