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With the tremendous success of deep learning, there exists imminent need todeploy deep learning models onto edge devices. To tackle the limited computingand storage resources in edge devices, model compression techniques have beenwidely used to trim deep neural network (DNN) models for on-device inferenceexecution. This paper targets the commonly used FPGA (field programmable gatearray) devices as the hardware platforms for DNN edge computing. We focus onthe DNN quantization as the main model compression technique, since DNNquantization has been of great importance for the implementations of DNN modelson the hardware platforms. The novelty of this work comes in twofold: (i) Wepropose a mixed-scheme DNN quantization method that incorporates both thelinear and non-linear number systems for quantization, with the aim to boostthe utilization of the heterogeneous computing resources, i.e., LUTs (look uptables) and DSPs (digital signal processors) on an FPGA. Note that all theexisting (single-scheme) quantization methods can only utilize one type ofresources (either LUTs or DSPs for the MAC (multiply-accumulate) operations indeep learning computations. (ii) We use a quantization method that supportsmultiple precisions along the intra-layer dimension, while the existingquantization methods apply multi-precision quantization along the inter-layerdimension. The intra-layer multi-precision method can uniform the hardwareconfigurations for different layers to reduce computation overhead and at thesame time preserve the model accuracy as the inter-layer approach.

MSP: An FPGA-Specific Mixed-Scheme, Multi-Precision Deep Neural Network Quantization Framework