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This paper presents several new structures to pursue high-resolution (< 2 ps)time-to-digital converters (TDCs) in Xilinx 20 nm UltraScale field-programmablegate arrays (FPGAs). The proposed TDCs combined the advantages of 1) our newlyproposed sub-tapped delay line (sub-TDL) architecture effective in removingbubbles and zero-bins and 2) the wave union (WU) A method to improve theresolution and reduce the impact introduced from ultrawide bins. We alsocompared the proposed WU/sub-TDL TDC with the TDC combining the dual sampling(DS) structure and the sub-TDL technique. Moreover, we introduced a binningmethod to improve the linearity and derived a formula of the total measurementuncertainty for a single-stage TDL-TDC to obtain its root-mean-square (RMS)resolution. Results conclude that the proposed designs are cost-effective inlogic resources and have the potential for multiple-channel implementations.Different from the conclusions from a previous study, we found that the waveunion is still influential in UltraScale devices when combining with oursub-TDL structure. We also compared with other published TDCs to demonstratewhere the proposed TDCs stand.

Are wave union methods still suitable for 20 nm FPGA-based high-resolution (< 2 ps) time-to-digital converters?