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Overlays are virtual, re-configurable architectures that overlay on top ofphysical FPGA fabrics. An overlay that is specialized for an application, or aclass of applications, offers both fast reconfiguration and minimizedperformance penalty. Such an overlay is usually implemented by hardwaredesigners in hardware "assembly" languages at register-transfer level (RTL).  This short article proposes an idea for a software programmer, instead ofhardware designers, to quickly implement an application-specific overlay usinghigh-level customizable IPs. These IPs are expressed succinctly by aspecification language, whose abstraction level is much higher than RTL but cannonetheless expresses many performance-critical loop and data optimizations onFPGAs, and thus would offer competitively high performance at a much lower costof maintenance and much easier customizations.  We propose new language features to easily put the IPs together into anoverlay. A compiler automatically implements the specified optimizations togenerate an efficient overlay, exposes a multi-tasking programming interfacefor the overlay, and inserts a runtime scheduler for scheduling tasks to run onthe IPs of the overlay, respecting the dependences between the tasks. While anapplication written in any language can take advantage of the overlay throughthe programming interface, we show a particular usage scenario, where theapplication itself is also succinctly specified in the same language.  We describe the new language features for expressing overlays, and illustratethe features with an LU decomposer and a convolutional neural network. A systemis under construction to implement the language features and workloads.

Building Application-Specific Overlays on FPGAs with High-Level Customizable IPs