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Data-parallel problems demand ever growing floating-point (FP) operations persecond under tight area- and energy-efficiency constraints. In this work, wepresent Manticore, a general-purpose, ultra-efficient chiplet-basedarchitecture for data-parallel FP workloads. We have manufactured a prototypeof the chiplet's computational core in Globalfoundries 22FDX process anddemonstrate more than 5x improvement in energy efficiency on FP intensiveworkloads compared to CPUs and GPUs. The compute capability at high energy andarea efficiency is provided by Snitch clusters containing eight small integercores, each controlling a large FPU. The core supports two custom ISAextensions: The SSR extension elides explicit load and store instructions byencoding them as register reads and writes. The FREP extension decouples theinteger core from the FPU allowing floating-point instructions to be issuedindependently. These two extensions allow the single-issue core to minimize itsinstruction fetch bandwidth and saturate the instruction bandwidth of the FPU,achieving FPU utilization above 90%, with more than 40% of core area dedicatedto the FPU.

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing