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The rapidly growing computational demands of deep neural networks requirenovel hardware designs. Recently, tunable nanoelectronic devices were developedbased on hopping electrons through a network of dopant atoms in silicon. These"Dopant Network Processing Units" (DNPUs) are highly energy-efficient and havepotentially very high throughput. By adapting the control voltages applied toits terminals, a single DNPU can solve a variety of linearly non-separableclassification problems. However, using a single device has limitations due tothe implicit single-node architecture. This paper presents a promising novelapproach to neural information processing by introducing DNPUs as high-capacityneurons and moving from a single to a multi-neuron framework. By implementingand testing a small multi-DNPU classifier in hardware, we show thatfeed-forward DNPU networks improve the performance of a single DNPU from 77% to94% test accuracy on a binary classification task with concentric classes on aplane. Furthermore, motivated by the integration of DNPUs with memristorarrays, we study the potential of using DNPUs in combination with linearlayers. We show by simulation that a single-layer MNIST classifier with only 10DNPUs achieves over 96% test accuracy. Our results pave the road towardshardware neural-network emulators that offer atomic-scale informationprocessing with low latency and energy consumption.

Dopant Network Processing Units: Towards Efficient Neural-network Emulators with High-capacity Nanoelectronic Nodes