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With the increasing awareness of privacy protection and data fragmentationproblem, federated learning has been emerging as a new paradigm of machinelearning. Federated learning tends to utilize various privacy preservingmechanisms to protect the transferred intermediate data, among whichhomomorphic encryption strikes a balance between security and ease ofutilization. However, the complicated operations and large operands imposesignificant overhead on federated learning. Maintaining accuracy and securitymore efficiently has been a key problem of federated learning. In this work, weinvestigate a hardware solution, and design an FPGA-based homomorphicencryption framework, aiming to accelerate the training phase in federatedlearning. The root complexity lies in searching for a compact architecture forthe core operation of homomorphic encryption, to suit the requirement offederated learning about high encryption throughput and flexibility ofconfiguration. Our framework implements the representative Paillier homomorphiccryptosystem with high level synthesis for flexibility and portability, withcareful optimization on the modular multiplication operation in terms ofprocessing clock cycle, resource usage and clock frequency. Our acceleratorachieves a near-optimal execution clock cycle, with a better DSP-efficiencythan existing designs, and reduces the encryption time by up to 71% duringtraining process of various federated learning models.

FPGA-Based Hardware Accelerator of Homomorphic Encryption for Efficient Federated Learning