English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Hyperdimensional computing (HD) is an emerging paradigm for machine learningbased on the evidence that the brain computes on high-dimensional, distributed,representations of data. The main operation of HD is encoding, which transfersthe input data to hyperspace by mapping each input feature to a hypervector,accompanied by so-called bundling procedure that simply adds up thehypervectors to realize encoding hypervector. Although the operations of HD arehighly parallelizable, the massive number of operations hampers the efficiencyof HD in embedded domain. In this paper, we propose SHEARer, analgorithm-hardware co-optimization to improve the performance and energyconsumption of HD computing. We gain insight from a prudent scheme ofapproximating the hypervectors that, thanks to inherent error resiliency of HD,has minimal impact on accuracy while provides high prospect for hardwareoptimization. In contrast to previous works that generate the encodinghypervectors in full precision and then ex-post quantizing, we compute theencoding hypervectors in an approximate manner that saves a significant amountof resources yet affords high accuracy. We also propose a novel FPGAimplementation that achieves striking performance through massive parallelismwith low power consumption. Moreover, we develop a software framework thatenables training HD models by emulating the proposed approximate encodings. TheFPGA implementation of SHEARer achieves an average throughput boost of 104,904x(15.7x) and energy savings of up to 56,044x (301x) compared to state-of-the-artencoding methods implemented on Raspberry Pi 3 (GeForce GTX 1080 Ti) usingpractical machine learning datasets.

SHEARer: Highly-Efficient Hyperdimensional Computing by Software-Hardware Enabled Multifold Approximation