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Deep Separable Convolutional Neural Networks (DSCNNs) have become theemerging paradigm by offering modular networks with structural sparsity inorder to achieve higher accuracy with relatively lower operations andparameters. However, there is a lack of customized architectures that canprovide flexible solutions that fit the sparsity of the DSCNNs. This paperintroduces DeepDive, which is a fully-functional, vertical co-design framework,for power-efficient implementation of DSCNNs on edge FPGAs. DeepDive'sarchitecture supports crucial heterogeneous Compute Units (CUs) to fullysupport DSCNNs with various convolutional operators interconnected withstructural sparsity. It offers an FPGA-aware training and online quantizationcombined with modular synthesizable C++ CUs, customized for DSCNNs. Theexecution results on Xilinx's ZCU102 FPGA board, demonstrate 47.4 and 233.3FPS/Watt for MobileNet-V2 and a compact version of EfficientNet, respectively,as two state-of-the-art depthwise separable CNNs. These comparisons showcasehow DeepDive improves FPS/Watt by 2.2$\times$ and 1.51$\times$ over Jetson Nanohigh and low power modes, respectively. It also enhances FPS/Watt about2.27$\times$ and 37.25$\times$ over two other FPGA implementations. TheDeepDive output for MobileNetV2 is available athttps://github.com/TeCSAR-UNCC/DeepDive.

DeepDive: An Integrative Algorithm/Architecture Co-Design for Deep Separable Convolutional Neural Networks