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We define a simple process calculus, based on Hennessy and Regan's TimedProcess Language, for specifying networks of communicating programmable logiccontrollers (PLCs) enriched with monitors enforcing specifications compliance.We define a synthesis algorithm that given an uncorrupted PLC returns a monitorthat enforces the correctness of the PLC, even when injected with malware thatmay forge/drop actuator commands and inter-controller communications. Then, westrengthen the capabilities of our monitors by allowing the insertion ofactions to mitigate malware activities. This gives us deadlock-freedommonitoring: malware may not drag monitored controllers into deadlock states.

A process calculus approach to correctness enforcement of PLCs (full version)