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Memory load/store instructions consume an important part in execution timeand energy consumption in domain-specific accelerators. For designing highlyparallel systems, available parallelism at each granularity is extracted fromthe workloads. The maximal use of parallelism at each granularity in thesehigh-performance designs requires the utilization of multi-port memories.Currently, true multiport designs are less popular because there is no inherentEDA support for multiport memory beyond 2-ports, utilizing more ports requirescircuit-level implementation and hence a high design time. In this work, wepresent a framework for Design Space Exploration of Algorithmic Multi-PortMemories (AMM) in ASICs. We study different AMM designs in the literature,discuss how we incorporate them in the Pre-RTL Aladdin Framework with differentmemory depth, port configurations and banking structures. From our analysis onselected applications from the MachSuite (accelerator benchmark suite), weunderstand and quantify the potential use of AMMs (as true multiport memories)for high performance in applications with low spatial locality in memory accesspatterns.

Design Space Exploration of Algorithmic Multi-Port Memories in High-Performance Application-Specific Accelerators