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GPGPU architectures have become established as the dominant parallelizationand performance platform achieving exceptional popularization and empoweringdomains such as regular algebra, machine learning, image detection andself-driving cars. However, irregular applications struggle to fully realizeGPGPU performance as a result of control flow divergence and memory divergencedue to irregular memory access patterns.  To ameliorate these issues, programmers are obligated to carefully considerarchitecture features and devote significant efforts to modify the algorithmswith complex optimization techniques, which shift programmers priorities yetstruggle to quell the shortcomings. We show that in graph-based GPGPU irregularapplications these inefficiencies prevail, yet we find that it is possible torelax the strict relationship between thread and data processed to empower newoptimizations.  Based on this key idea, we propose the Irregular accesses Reorder Unit (IRU),a novel hardware extension tightly integrated in the GPGPU pipeline. The IRUreorders data processed by the threads on irregular accesses whichsignificantly improves memory coalescing, and allows increased performance andenergy efficiency. Additionally, the IRU is capable of filtering and mergingduplicated irregular access which further improves graph-based irregularapplications. Programmers can easily utilize the IRU with a simple API, orcompiler optimized generated code with the extended ISA instructions provided.  We evaluate our proposal for state-of-the-art graph-based algorithms and awide selection of applications. Results show that the IRU achieves a memorycoalescing improvement of 1.32x and a 46% reduction in the overall traffic inthe memory hierarchy, which results in 1.33x and 13% improvement in performanceand energy savings respectively, while incurring in a small 5.6% area overhead.

Irregular Accesses Reorder Unit: Improving GPGPU Memory Coalescing for Graph-Based Workloads