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Hardware-enclaves that target complex CPU designs compromise both securityand performance. Programs have little control over micro-architecture, whichleads to side-channel leaks, and then have to be transformed to have worst-casecontrol- and data-flow behaviors and thus incur considerable slowdown. Wepropose to address these security and performance problems by bringing enclavesinto the realm of accelerator-rich architectures. The key idea is to constructsoftware-defined enclaves (SDEs) where the protections and slowdown are tied toan application-defined threat model and tuned by a compiler for theaccelerator's specific domain. This vertically integrated approach requires newhardware data-structures to partition, clear, and shape the utilization ofhardware resources; and a compiler that instantiates and schedules thesedata-structures to create multi-tenant enclaves on accelerators. We demonstrateour ideas with a comprehensive prototype -- Sesame -- that includesmodifications to compiler, ISA, and microarchitecture to a decoupled accessexecute (DAE) accelerator framework for deep learning models. Our securityevaluation shows that classifiers that could distinguish different layers inVGG, ResNet, and AlexNet, fail to do so when run using Sesame. Oursynthesizable hardware prototype (on a Xilinx Pynq board) demonstrates how thecompiler and micro-architecture enables threat-model-specific trade-offs incode size increase ranging from 3-7 $\%$ and run-time performance overhead forspecific defenses ranging from 3.96$\%$ to 34.87$\%$ (across confidentialinputs and models and single vs. multi-tenant systems).

SESAME: Software defined Enclaves to Secure Inference Accelerators with Multi-tenant Execution