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With data-driven analytics becoming mainstream, the global demand fordedicated AI and Deep Learning accelerator chips is soaring. Theseaccelerators, designed with densely packed Processing Elements (PE), areespecially vulnerable to the manufacturing defects and functional faults commonin the advanced semiconductor process nodes resulting in significant yieldloss. In this work, we demonstrate an application-driven methodology of binningthe AI accelerator chips, and yield loss reduction by correlating the circuitfaults in the PEs of the accelerator with the desired accuracy of the target AIworkload. We exploit the inherent fault tolerance features of trained deeplearning models and a strategy of selective deactivation of faulty PEs todevelop the presented yield loss reduction and test methodology. An analyticalrelationship is derived between fault location, fault rate, and the AI task'saccuracy for deciding if the accelerator chip can pass the final yield test. Ayield-loss reduction aware fault isolation, ATPG, and test flow are presentedfor the multiply and accumulate units of the PEs. Results obtained with widelyused AI/deep learning benchmarks demonstrate that the accelerators can sustain5% fault-rate in PE arrays while suffering from less than 1% accuracy loss,thus enabling product-binning and yield loss reduction of these chips.

Yield Loss Reduction and Test of AI and Deep Learning Accelerators