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In order to shed more light on how RowHammer affects modern and futuredevices at the circuit-level, we first present an experimental characterizationof RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4, and 520x LPDDR4) from300 DRAM modules (60x DDR3, 110x DDR4, and 130x LPDDR4) with RowHammerprotection mechanisms disabled, spanning multiple different technology nodesfrom across each of the three major DRAM manufacturers. Our studiesdefinitively show that newer DRAM chips are more vulnerable to RowHammer: asdevice feature size reduces, the number of activations needed to induce aRowHammer bit flip also reduces, to as few as 9.6k (4.8k to two rows each) inthe most vulnerable chip we tested.  We evaluate five state-of-the-art RowHammer mitigation mechanisms usingcycle-accurate simulation in the context of real data taken from our chips tostudy how the mitigation mechanisms scale with chip vulnerability. We find thatexisting mechanisms either are not scalable or suffer from prohibitively largeperformance overheads in projected future devices given our observed trends ofRowHammer vulnerability. Thus, it is critical to research more effectivesolutions to RowHammer.

Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques