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DRAM is the prevalent main memory technology, but its long access latency canlimit the performance of many workloads. Although prior works provide DRAMdesigns that reduce DRAM access latency, their reduced storage capacitieshinder the performance of workloads that need large memory capacity. Becausethe capacity-latency trade-off is fixed at design time, previous works cannotachieve maximum performance under very different and dynamic workload demands.  This paper proposes Capacity-Latency-Reconfigurable DRAM (CLR-DRAM), a newDRAM architecture that enables dynamic capacity-latency trade-off at low cost.CLR-DRAM allows dynamic reconfiguration of any DRAM row to switch between twooperating modes: 1) max-capacity mode, where every DRAM cell operatesindividually to achieve approximately the same storage density as adensity-optimized commodity DRAM chip and 2) high-performance mode, where twoadjacent DRAM cells in a DRAM row and their sense amplifiers are coupled tooperate as a single low-latency logical cell driven by a single logical senseamplifier.  We implement CLR-DRAM by adding isolation transistors in each DRAM subarray.Our evaluations show that CLR-DRAM can improve system performance and DRAMenergy consumption by 18.6% and 29.7% on average with four-core multiprogrammedworkloads. We believe that CLR-DRAM opens new research directions for a systemto adapt to the diverse and dynamically changing memory capacity and accesslatency demands of workloads.

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off