English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

We show that the quantum parity gate on $n > 3$ qubits cannot be cleanlysimulated by a quantum circuit with two layers of arbitrary C-SIGN gates of anyarity and arbitrary 1-qubit unitary gates, regardless of the number of allowedancilla qubits. This is the best known and first nontrivial separation betweenthe parity gate and circuits of this form. The same bounds also apply to thequantum fanout gate. Our results are incomparable with those of Fang et al.[3], which apply to any constant depth but require a sublinear number ofancilla qubits on the simulating circuit.

Depth-2 QAC circuits cannot simulate quantum parity