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Traditional von Neumann architecture based processors become inefficient interms of energy and throughput as they involve separate processing and memoryunits, also known as~\textit{memory wall}. The memory wall problem is furtherexacerbated when massive parallelism and frequent data movement are requiredbetween processing and memory units for real-time implementation of artificialneural network (ANN) that enables many intelligent applications. One of themost promising approach to address the memory wall problem is to carry outcomputations inside the memory core itself that enhances the memory bandwidthand energy efficiency for extensive computations. This paper presents anin-memory computing architecture for ANN enabling artificial intelligence (AI)and machine learning (ML) applications. The proposed architecture utilizes deepin-memory architecture based on standard six transistor (6T) static randomaccess memory (SRAM) core for the implementation of a multi-layered perceptron.Our novel on-chip training and inference in-memory architecture reduces energycost and enhances throughput by simultaneously accessing the multiple rows ofSRAM array per precharge cycle and eliminating the frequent access of data. Theproposed architecture realizes backpropagation which is the keystone during thenetwork training using newly proposed different building blocks such as weightupdation, analog multiplication, error calculation, signed analog to digitalconversion, and other necessary signal control units. The proposed architecturewas trained and tested on the IRIS dataset which exhibits $\approx46\times$more energy efficient per MAC (multiply and accumulate) operation compared toearlier classifiers.

In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications