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Clockwise to anti-clockwise hysteresis crossover in current-voltage transfercharacteristics of field effect transistors (FETs) with graphene and MoS$_2$channels holds significant promise for non-volatile memory applications.However such crossovers have been shown to manifest only at high temperature.In this work, for the first time, we demonstrate room temperature hysteresiscrossover in few-layer MoS$_2$ FETs by using a gate-drain underlap design toinduce a differential response from traps at the MoS$_2$-HfO$_2$ channel-gatedielectric interface to applied gate bias. The appearance of interfacetrap-driven anti-clockwise hysteresis at high gate voltages in underlap FETscan be unambiguously attributed to the presence of an underlap sincetransistors with and without the underlap region were fabricated on the sameMoS$_2$ channel flake. The underlap design also enables room temperature tuningof the anti-clockwise hysteresis window (by 140$\times$) as well as thecrossover gate voltage (by 2.6$\times$) with applied drain bias and underlaplength. Comprehensive measurements of the transfer curves in ambient and vacuumconditions at varying sweep rates and temperatures (RT, 45 $^\circ$C and 65$^\circ$C) help segregate the quantitative contributions of adsorbates,interface traps, and bulk HfO$_2$ traps to the clockwise and anti-clockwisehysteresis.

Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS$_2$ FETs