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We empirically evaluate an undervolting technique, i.e., underscaling thecircuit supply voltage below the nominal level, to improve the power-efficiencyof Convolutional Neural Network (CNN) accelerators mapped to Field ProgrammableGate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timingfaults due to excessive circuit latency increase. We evaluate thereliability-power trade-off for such accelerators. Specifically, weexperimentally study the reduced-voltage operation of multiple components ofreal FPGAs, characterize the corresponding reliability behavior of CNNaccelerators, propose techniques to minimize the drawbacks of reduced-voltageoperation, and combine undervolting with architectural CNN optimizationtechniques, i.e., quantization and pruning. We investigate the effect ofenvironmental temperature on the reliability-power trade-off of suchaccelerators. We perform experiments on three identical samples of modernXilinx ZCU102 FPGA platforms with five state-of-the-art image classificationCNN benchmarks. This approach allows us to study the effects of ourundervolting technique for both software and hardware variability. We achievemore than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gainis the result of eliminating the voltage guardband region, i.e., the safevoltage region below the nominal level that is set by FPGA vendor to ensurecorrect functionality in worst-case environmental and circuit conditions. 43%of the power-efficiency gain is due to further undervolting below theguardband, which comes at the cost of accuracy loss in the CNN accelerator. Weevaluate an effective frequency underscaling technique that prevents thisaccuracy loss, and find that it reduces the power-efficiency gain from 43% to25%.

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration