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Automatic transistor sizing is a challenging problem in circuit design due tothe large design space, complex performance trade-offs, and fast technologicaladvancements. Although there has been plenty of work on transistor sizingtargeting on one circuit, limited research has been done on transferring theknowledge from one circuit to another to reduce the re-design overhead. In thispaper, we present GCN-RL Circuit Designer, leveraging reinforcement learning(RL) to transfer the knowledge between different technology nodes andtopologies. Moreover, inspired by the simple fact that circuit is a graph, welearn on the circuit topology representation with graph convolutional neuralnetworks (GCN). The GCN-RL agent extracts features of the topology graph whosevertices are transistors, edges are wires. Our learning-based optimizationconsistently achieves the highest Figures of Merit (FoM) on four differentcircuits compared with conventional black-box optimization methods (BayesianOptimization, Evolutionary Algorithms), random search, and human expertdesigns. Experiments on transfer learning between five technology nodes and twocircuit topologies demonstrate that RL with transfer learning can achieve muchhigher FoMs than methods without knowledge transfer. Our transferableoptimization method makes transistor sizing and design porting more effectiveand efficient.

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning