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Recently, a parallel decoding algorithm of $G_N$-coset codes was proposed.Thealgorithm exploits two equivalent decoding graphs.For each graph, the innercode part, which consists of independent component codes, is decoded inparallel. The extrinsic information of the code bits is obtained anditeratively exchanged between the graphs until convergence. This algorithmenjoys a higher decoding parallelism than the previous successive cancellationalgorithms, due to the avoidance of serial outer code processing. In this work,we present a hardware implementation of the parallel decoding algorithm, it cansupport maximum $N=16384$. We complete the decoder's physical layout in TSMC$16nm$ process and the size is $999.936\mu m\times 999.936\mu m, \,\approx1.00mm^2$. The decoder's area efficiency and power consumption are evaluatedfor the cases of $N=16384,K=13225$ and $N=16384, K=14161$. Scaled to $7nm$process, the decoder's throughput is higher than $477Gbps/mm^2$ and$533Gbps/mm^2$ with five iterations.

Toward Terabits-per-second Communications: A High-Throughput Hardware Implementation of $G_N$-Coset Codes