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The steeply growing performance demands for highly power- andenergy-constrained processing systems such as end-nodes of theinternet-of-things (IoT) have led to parallel near-threshold computing (NTC),joining the energy-efficiency benefits of low-voltage operation with theperformance typical of parallel systems. Shared-L1-memory multiprocessorclusters are a promising architecture, delivering performance in the order ofGOPS and over 100 GOPS/W of energy-efficiency. However, this level ofcomputational efficiency can only be reached by maximizing the effectiveutilization of the processing elements (PEs) available in the clusters. Alongwith this effort, the optimization of PE-to-PE synchronization andcommunication is a critical factor for performance. In this work, we describe alight-weight hardware-accelerated synchronization and communication unit (SCU)for tightly-coupled clusters of processors. We detail the architecture, whichenables fine-grain per-PE power management, and its integration into aneight-core cluster of RISC-V processors. To validate the effectiveness of theproposed solution, we implemented the eight-core cluster in advanced 22nm FDXtechnology and evaluated performance and energy-efficiency with tunablemicrobenchmarks and a set of real-life applications and kernels. The proposedsolution allows synchronization-free regions as small as 42 cycles, over 41times smaller than the baseline implementation based on fast test-and-setaccess to L1 memory when constraining the microbenchmarks to 10%synchronization overhead. When evaluated on the real-life DSP-applications, theproposed SCU improves performance by up to 92% and 23% on average and energyefficiency by up to 98% and 39% on average.

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters